Pseudo SRAM (PSRAM) which is based on DRAM has long been widely used in battery-driven products, such as cell phones and PDAs, particularly in products which require a large amount of memory capacity and thus are difficult to be realized with conventional SRAM. It is important for PSRAM not only to have a large memory capacity but also to achieve reduction in electric current in both standby and active modes. Furthermore, along with improvements in functions and performance of apparatuses in which PSRAM is to be used, it has become important in recent years for PSRAM to achieve increase in speed. For example, in an asynchronous system with conventional interface using SRAM, page mode with cycle time as short as 15 ns-20 ns is used. In order to achieve further increase in speed, in synchronous systems, products capable of performing writes and reads in 4-, 8-, and 16-word burst modes with a clock of 75 MHz and above 100 MHz have started to emerge. As a result, PSRAMs are advancing to be products encompasing more SDRAM-like qualities than SRAMs.
In standard PSRAM specifications (e.g., COSMORAM and Cellular RAM), the data rate of each burst of writes or reads in burst mode is high. However, in burst modes, a subsequent write or read command cannot be entered until after each burst ends. Therefore, when consecutive burst writes or reads of 4-, 8-, and 16-words are performed, an interval occurs between bursts on data bus. As a result, the data rate for consecutive burst operations becomes considerably lower than the maximum data rate which is determined by the clock being used.
FIGS. 1A and 1B are timing charts showing the operations of 4-word burst length in conventional PSRAM. FIGS. 1A and 1B show an example of the case in which the write latency is 4 and the read latency is 5 which are based on standard specifications. FIG. 1A shows two consecutive burst write operations. An address (ADR) is provided at a clock (CLK) timing (t1) at which the chip enabling (CE) signal, the address valid (ADV) signal , and the write enabling (WE) signal are low and the output enabling (OE) signal is high, so the first write command is entered. Then, from the fourth clock (t2) after that timing, 4-word burst data is provided to the data I/O. ATC represents an array time constant which indicates the time interval from the time point when word lines in the memory array start to be activated (high) to the time point when the operation of the memory array ends (bit lines are equalized). In pipeline systems such as used in SDRAM, the memory array is kept activated during the burst. Thus, until after the 4-word write completes, the subsequent write command cannot be entered. Accordingly, the subsequent write command is entered at the third clock (t3) from the last clock of the burst.
FIG. 1B shows two consecutive burst read operations. An address (ADR) is provided at a clock timing (t4) at which CE, ADV, and OE signals are low and the WE signal is high, so the first read command is entered. Then, from the fifth clock (t5), 4-word data are outputted to the data I/O. As with the write shown in FIG. 1A, in the pipeline operation, the memory array is kept activated until the last burst data is outputted. Accordingly, the subsequent read command cannot be entered until after the activated memory array is restored. Therefore, the subsequent read command is entered at the second clock (t6) from the clock of the last burst data. In the conventional PSRAM shown in FIGS. 1A and 1B, in both write and read, 6 clock interval (t1) occurs between bursts at the data I/O. That is, the data I/O repeats, for each burst operation, the operation of conveying consecutive data corresponding to four clocks and then no acitivies for six clocks. Thus, the data rate for the consecutive bursts is only 40% of the maximum data rate that is determined by the clock.
As a method of increasing the burst data rate, there is a general method as used in SDRAMs in which by providing a plurality of banks, seamlessness is achieved between bursts by bank interleaving. This method, however, has a problem that when consecutive accesses are made to an identical bank, seamlessness cannot be achieved.
A method that solves such problems is disclosed in Japanese Patent Publication No. 3362775 (corresponding to U.S. Pat. No. 6,252,794) assigned to the present assignee and herein incorporated by reference. This publication proposes a method that allows a seamless operation in all random row accesses including accesses to an identical bank. According to the method, during a write operation, burst data are sequentially latched (preloaded) and when all burst data are latched, all burst data are written to the memory cell array at the same time. During a read operation, all burst data are prefetched in a set of latches at a time after the sense amplifiers are first activated. The method employs a scheme in which activation of the array is done only for a single burst and precharging is performed immediately after the burst for both the read and write operations.
However, even if the method disclosed in the '794 patent is used, the following problem remains. Standard specifications define the aforementioned timings as shown in FIGS. 1A and 1B, and the second and subsequent write or read commands are specified to be entered at a time when the last burst ends. Therefore, as long as the standard command input scheme is used, even if the preload and prefetch scheme described in the aforementioned patent is used, the seamless input and output of consecutive burst data cannot be achieved. In other words, the data rate for consecutive bursts cannot be improved. Hence, a novel method is required that enables seamless operations without violating standard specifications as well as the operations conforming to the specifications.